Abschlussarbeit am IAS: Low Power Design of a High Speed DSP
Verfasst: Do 21. Apr 2011, 13:02
Hallo zusammen,
es gibt wieder neue Interessante Abschlussarbeiten am IAS, z.B.:
Low Power Design of a High Speed DSP Block for a Multistandard Transmitter
http://www.ias.rwth-aachen.de/fileadmin ... plevel.pdf
Chair of Integrated Analog Circuits is developing transmitter ASICs for next generation mobile handsets, in cooperation with UMIC excellence cluster. The transmitters will be capable of supporting novel standards as LTE or WLAN as well as legacy standards as GSM or UMTS. To support the wide range of requirements the transmitter needs a fully reconfigurable high speed digital signal processing block. At the same time power dissipation should be as low as possible to save battery time.
Bei Interesse einfach bei mir melden.
Schönen Gruß,
Bastian
es gibt wieder neue Interessante Abschlussarbeiten am IAS, z.B.:
Low Power Design of a High Speed DSP Block for a Multistandard Transmitter
http://www.ias.rwth-aachen.de/fileadmin ... plevel.pdf
Chair of Integrated Analog Circuits is developing transmitter ASICs for next generation mobile handsets, in cooperation with UMIC excellence cluster. The transmitters will be capable of supporting novel standards as LTE or WLAN as well as legacy standards as GSM or UMTS. To support the wide range of requirements the transmitter needs a fully reconfigurable high speed digital signal processing block. At the same time power dissipation should be as low as possible to save battery time.
Bei Interesse einfach bei mir melden.
Schönen Gruß,
Bastian